Collaborating with a leading hardware company to develop cutting-edge compilers for RISC-V architectures with custom instruction sets. Designed comprehensive programming models, frameworks, libraries, and APIs for packet and protocol processing.
The Challenge
Emerging RISC-V architectures with custom instruction set extensions require specialized compiler toolchains that do not exist off the shelf. The target hardware handles high-throughput packet processing, demanding compilers that can exploit custom instructions for networking workloads.
Our Approach
We are extending the LLVM compiler infrastructure with custom backends for RISC-V ISA extensions, including instruction selection, register allocation, and scheduling passes optimized for packet processing. The toolchain includes a custom programming model, framework libraries, and APIs that abstract the hardware complexity for application developers.
Results
The compiler toolchain enables developers to target custom RISC-V hardware without writing assembly, generating optimized code that leverages proprietary instruction extensions for wire-speed packet processing.